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september 2012 doc id 022726 rev 2 1/60 AN4043 application note sllimm?-nano small low-loss intelligent molded module by carmelo parisi and giovanni tomasello introduction in recent years the variable speed motor control market has required high performance solutions able to satisfy the increasing energy saving requirements, compactness, reliability, and system costs in home appliances, such as dish washers, refrigerator compressors, air conditioning fans, draining and recirculation pumps, and in low power industrial applications, such as small fans, pumps and tools, etc. to meet these market needs, stmicroelectronics has developed a new family of very compact, high efficiency, dual-in-line intelligent power modules, with optional extra features, called small low-loss intelligent molded module nano (sllimm?-nano). the sllimm-nano product family combines optimized silicon chips, integrated in three main inverter blocks: power stage ? six very fast igbts ? six freewheeling diodes driving network ? three high voltage gate drivers ? three gate resistors ? three bootstrap diodes protection and optional features ? op amp for advanced current sensing ? comparator for fault protection against overcurrent and short-circuit ? smart shutdown function ? dead time, interlocking function and undervoltage lockout. thanks to its very good compactness, the fully isolated sllimm-nano package (ndip) is the ideal solution for applications requiring reduced assembly space, without sacrificing thermal performance and reliability. compared to discrete-based inverters, including power devices, and driver and protection circuits, the sllimm-nano family provides a high integrated level that means simplified circuit design, reduced component count, lower weight, and high reliability. the aim of this application note is to provide a detailed description of sllimm-nano products, providing guidelines to motor drive designers for an efficient, reliable, and fast design when using the new st sllimm-nano family. www.st.com
contents AN4043 2/60 doc id 022726 rev 2 contents 1 inverter design concept and sllimm-nano solution . . . . . . . . . . . . . . . 5 1.1 product synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 product line-up and nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3 internal circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 electrical characteristics and functions . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 igbts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 freewheeling diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 high voltage gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.1 logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.2 high voltage level shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.3 undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.4 dead time and interlocking function management . . . . . . . . . . . . . . . . . 19 2.3.5 comparators for fault sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.6 short-circuit protection and smart shutdown function . . . . . . . . . . . . . . 22 2.3.7 timing chart of short-circuit protection and smart shutdown function . . 23 2.3.8 current sensing shunt resistor selection . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.9 rc filter network selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3.10 op amps for advanced current sensing . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3.11 bootstrap circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3.12 bootstrap capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.3.13 initial bootstrap capacitor charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.1 package structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.2 package outline and dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.3 input and output pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4 power losses and dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.1 conduction power losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.2 switching power losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.3 thermal impedance overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
AN4043 contents doc id 022726 rev 2 3/60 4.4 power loss calculation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5 design and mounting guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.1 layout suggestions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.1.1 general suggestions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.2 mounting instructions and cooling techniques . . . . . . . . . . . . . . . . . . . . . 53 6 general handling precaution and storage notices . . . . . . . . . . . . . . . . 56 6.1 packaging specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
list of tables AN4043 4/60 doc id 022726 rev 2 list of tables table 1. sllimm-nano line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2. inverter part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. control part of the stgipn3h60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4. supply voltage and operation behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5. total system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 6. integrated pull-up/down resistor values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 table 7. interlocking function truth table of the stgipn3h60a . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8. interlocking function truth table of the stgipn3h60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 9. outline drawing of ndip-26l package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 10. input and output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 11. cauer and foster rc thermal network elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 12. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
AN4043 list of figures doc id 022726 rev 2 5/60 list of figures figure 1. inverter motor drive block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. discrete-based inverter vs. sllimm-nano solution comparison. . . . . . . . . . . . . . . . . . . . . . 7 figure 3. sllimm block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. sllimm-nano nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. internal circuit of the stgipn3h60a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. internal circuit of the stgipn3h60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7. stray inductance components of output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 8. high voltage gate drive die image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 9. high voltage gate driver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 figure 10. logic input configuration for the stgipn3h60a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 11. logic input configuration for the stgipn3h60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 12. timing chart of undervoltage lockout function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 13. timing chart of dead time function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 14. smart shutdown equivalent circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 15. timing chart of smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 figure 16. examples of sc protection circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 17. example of sc event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 18. 3-phase system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 19. general advanced current sense scheme and waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 20. bootstrap circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 21. bootstrap capacitor vs. switching frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 22. initial bootstrap charging time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 23. images and internal view of ndip-26l package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 24. outline drawing of ndip-26l package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 25. pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 26. typical igbt power losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 27. igbt and diode approximation of the output characteristics . . . . . . . . . . . . . . . . . . . . . . . 43 figure 28. typical switching waveforms of the stgipn3h60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 29. r th(j-a) equivalent thermal circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 30. thermal impedance z th(j-a) curve for a single igbt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 31. cauer rc equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 32. foster rc equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 33. maximum i c(rms) current vs. fsw simulated curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 34. general suggestions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 35. example 1 on a possible wrong layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 figure 36. example 2 on a possible wrong layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 figure 37. cooling technique: copper plate on the pcb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 38. cooling technique: heatsink bonded on the package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 39. cooling technique: heatsink bonded on the pcb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 40. packaging specifications of ndip-26l package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
inverter design concept and sllimm-nano solution AN4043 6/60 doc id 022726 rev 2 1 inverter design concept and sllimm-nano solution motor drive applications, ranging from a few tens of watts to mega watts, are mainly based on the inverter concept thanks to the fact that this solution can meet efficiency, reliability, size, and cost constraints required in a number of markets. as shown in figure 1 , an inverter for motor drive applications is basically composed of a power stage, mainly based on igbts and freewheeling diodes; a driving stage, based on high voltage gate drivers; a control unit, based on microcontrollers or dsps; some optional sensors for protection and feedback signals for controls. the approach of this solution with discrete devices produces high manufacturing costs associated with high reliability risks, bigger size and higher weight, a considerable number of components and the significant stray inductances and dispersions in the board layout. in recent years, the use of intelligent power modules has rapidly increased thanks to the benefits of greater integration levels. the new st sllimm-nano family is able to replace more than 20 discrete devices in a single package. figure 2 shows a comparison between a discrete-based inverter and the sllimm-nano solution, the advantages of sllimm-nano can be easily understood and can be summarized in a significantly improved design time, reduced manufacturing efforts, higher flexibility in a wide range of applications, and increased reliability and quality level. in addition, the optimized silicon chips in both control and power stages and the optimized board layout provide maximized efficiency, reduced emi and noise generation, higher levels of protection, and lower propagation delay time. figure 1. inverter motor drive block diagram *dwhgulyhu 3rzhuvwdjh 6hqvruv %ulgjhuhfwlilhu 0lfurfrqwuroohu 0 )hhgedfn 0dlqv !-v
AN4043 inverter design concept and sllimm-nano solution doc id 022726 rev 2 7/60 1.1 product synopsis the sllimm-nano family has been designed to satisfy the requirements of a wide range of final applications up to 100 w (in free air), such as: dish washers refrigerator compressors air conditioning fans draining and recirculation pumps low power industrial applications small fans, pumps and tools. the main features and integrated functions can be summarized as follows: 600 v, 3 a ratings 3-phase igbt inverter bridge including: ? six low-loss igbts ? six low forward voltage drop and soft recovery freewheeling diodes three control ics for gate driving and protection including: ? smart shutdown function ? comparator for fault protection against overcurrent and short-circuit ? op amp for advanced current sensing ? three integrated bootstrap diodes ? interlocking function ? undervoltage lockout open emitter configuration for individual phase current sensing very compact and fully isolated package integrated gate resistors for igbt switching speed optimum setting gate driver proper biasing. figure 2. discrete-based inverter vs. sllimm-nano solution comparison !-v 6//,00 q d qr 6//,00 q d qr (dv\od\rxw dqgghvljq 5hgxfhg(0, dqgqrlvh +ljktxdolw\ dqguholdelolw\ ,psuryhg hiilflhqf\ $gydqfhg sur whfwlrq ixqfwlrq 5hgxfhgwrwdo v\vwhpfrvw 3dvv lyhfrpsrqhqwv 'lrg hv 5hvlvwruv +9jdwhgulyhuv ,*%7v):'v +ljk frpsdfwqhvv
inverter design concept and sllimm-nano solution AN4043 8/60 doc id 022726 rev 2 figure 3 shows the block diagram of the sllimm-nano included in the inverter solution. the power devices (igbts and freewheeling diodes), incorporated in the half bridge block, are tailored for a motor drive application delivering the greatest overall efficiency, thanks to the optimized trade-off between conduction and switching power losses and very low emi generation, as a result of reduced dv/dt and di/dt. the ic gate drivers have been selected in order to meet two levels of functionality, giving users more freedom to choose: a basic version which includes the essential features for a cost-effective solution and a fully featured version which provides advanced options for a sophisticated control method. the fully isolated ndip package offers a high compactness level, very useful in those applications with reduced space, ensuring at the same time, high thermal performance and reliability levels. figure 3. sllimm block diagram !-v 6//,00qdqr *dwhgulyhu *dwhgulyhu *dwhgulyhu +doieulgjh 89/2 'hdgwlph /hyho 6kliw %rrwvwuds glrgh &rpsdudwru 6pduw 6kxw'rzq 2s$ps 89/2 'hdgwlph /hyho 6kliw %rrwvwuds glrgh &rpsdudwru 6pduw 6kxw'rzq 2s$ps 89/2 'hdgwlph /hyho 6kliw %rrwvwuds glrgh &rpsdudwru 6pduw 6kxw'rzq 2s$ps +doieulgjh +doieulgjh %ulgjhuhfwlilhu 0lfurfrqwuroohu 0 )hhgedfn 0dlqv
AN4043 inverter design concept and sllimm-nano solution doc id 022726 rev 2 9/60 1.2 product line-up and nomenclature table 1. sllimm-nano line-up features basic version fully featured version stgipn3h60a stgipn3h60 voltage (v) 600 600 current @ t c = 25 c (a) 3 3 r thja max. (c/w) 50 50 package type ndip-26l ndip-26l package size (mm) x, y, z 29.5x12.5x3.1 29.5x12.5x3.1 integrated bootstrap diode yes yes sd function no yes comparator for fault protection no yes (1 pin) smart shutdown function no yes op amps for advanced current sensing no yes interlocking function yes yes undervoltage lockout yes yes open emitter configuration yes (3 pins) yes (3 pins) 3.3 / 5 v input interface compatibility yes yes high-side igbt input signal active high active high low-side igbt input signal active high active low figure 4. sllimm-nano nomenclature !-v 67 * ,3 / . [ * - ,*%7'lrgh 6//,00?,30 3dfndjh / 6',3/proghg 1 1',3/ proghg 6 6',3/ proghg 1rplqdofxuuhqw , & fxuuhqwdw7 & ?& 7hfkqrorj\ .+ +ljkiuhtxhqf\n+] : 9hu\+ljkiuhtxhqf\n+] & 0hglxpiuhtxhqf\n+] 9 &(6 yrowdjhglylghge\ 6shfldoihdwxuhv $ %dvlfyhuvlrq / 6lqjohskdvh
inverter design concept and sllimm-nano solution AN4043 10/60 doc id 022726 rev 2 1.3 internal circuit figure 5. internal circuit of the stgipn3h60a
AN4043 inverter design concept and sllimm-nano solution doc id 022726 rev 2 11/60 1.4 absolute maximum ratings the absolute maximum ratings represent the extreme capability of the device and they can be normally used as a worst limit design condition. it is important to note that the absolute maximum value is given according to a set of testing conditions such us temperature, frequency, voltage, and so on. device performance can change according to the applied condition. figure 6. internal circuit of the stgipn3h60
inverter design concept and sllimm-nano solution AN4043 12/60 doc id 022726 rev 2 the sllimm-nano specifications are described below using the stgipn3h60 datasheet as an example. please refer to the respective product datasheets for a detailed description of all possible types. equation 1 v ces : collector emitter voltage the power stage of the sllimm-nano is based on igbts (and freewheeling diodes) having 600 v v ces rating. generally, considering the intelligent power module internal stray inductances during the commutations, which can generate some surge voltages, the maximum surge voltage between p-n (v pn(surge) ) allowed is lower than v ces , as shown in figure 7 . at the same time, considering also the surge voltage generated by the stray inductance between the device and the dc-link capacitor, the maximum supply voltage (in steady-state) applied between p-n (v pn ) must be even lower than v pn(surge) . thanks to the small package size and the lower working current, this phenomenon is less marked in the sllimm-nano than in a big intelligent power module. table 2. inverter part symbol parameter value unit v ces collector emitter voltage (v in (1) = 0) 1. applied between hin u , hin v , hin w ; lin u , lin v , lin w and gnd. 600 v i c (2) 2. calculated according to the iterative equation 1 . each igbt continuous collector current at t c = 25 c 3 a i c (3) 3. pulse width limited by max. junction temperature. each igbt pulsed collector current 18 a p tot each igbt total dissipation at t c = 25 c 8 w )) t ( i t (@ v r t t ) t ( i c c max, j )(max) sat ( ce ) c j ( th c max j c c ? ? = ?
AN4043 inverter design concept and sllimm-nano solution doc id 022726 rev 2 13/60 i c : each igbt continuous collector current the allowable dc current continuously flowing at the collector electrode (t c = 25 c). the i c parameter is calculated according to equation 1 . v cc : low voltage power supply figure 7. stray inductance components of output stage !-v 3dudvlwlflqgxfwdqfh gxhwr3&%od\rxw 3 1 89: +9,& 6//,00qdqr wrprwru 9 exv 9 exv 3dudvlwlflqgxfwdqfh gxhwrwkh6//,00lqwhuqdood\rxw 7khuhdoyrowdjhryhuwkh,*%7 fdqh[fhhgwkhudwlqjyrowdjh 'xhwrglgw ydox hdqgsdudvlwlf lqgxfwdqfhwkhryhuyrowdjhvslnh fdqdsshdurqwkh6//,00slqv 9 31vxujh +ljk glgw ydoxh )odw9 31 ydoxh 9 31 & table 3. control part of the stgipn3h60 symbol parameter value unit v out output voltage applied between out u , out v , out w , and gnd (v cc =15 v) v boot -21 to v boot +0.3 v v cc low voltage power supply -0.3 to 21 v v cin comparator input voltage -0.3 to v cc +0.3 v v op+ op amp non-inverting input -0.3 to v cc +0.3 v v op op amp inverting input -0.3 to v cc +0.3 v v boot bootstrap voltage -0.3 to 620 v v in logic input voltage applied between hin, lin and gnd -0.3 to 15 v v sd /od open drain voltage -0.3 to 15 v dv out /dt allowed output slew rate 50 v/ns
inverter design concept and sllimm-nano solution AN4043 14/60 doc id 022726 rev 2 v cc represents the supply voltage of the control part. a local filtering is recommended to enhance the sllimm-nano noise immunity. generally, the use of one electrolytic capacitor (with greater value but not negligible esr) and one smaller ceramic capacitor (hundreds of nf), faster than the electrolytic one to provide current, is suggested. please refer to ta b l e 4 in order to properly drive the sllimm-nano. table 4. supply voltage and operation behavior v cc voltage (typ. value) operating behavior stgipn3h60a stgipn3h60 < 10 v < 12 v as the voltage is lower than the uvlo threshold the control circuit is not fully turned on. a perfect functionality cannot be guaranteed. 12 v ? 17 v 13.5 v ? 18 v typical operating conditions > 18 v > 21 v control circuit is destroyed table 5. total system symbol parameter value unit t j operating junction temperature -40 to 150 c t c module case operation temperature -40 to 125 c
AN4043 electrical characteristics and functions doc id 022726 rev 2 15/60 2 electrical characteristics and functions in this section the main electrical characteristics of the power stage are discussed, together with a detailed description of all the sllimm-nano functions. 2.1 igbts the sllimm-nano achieves power savings in the inverter stage thanks to the use of igbts manufactured with the proprietary advanced powermesh? process. these power devices, optimized for the typical motor control switching frequency, offer an excellent trade-off between voltage drop (v ce(sat) ) and switching speed (t fall ), and therefore minimize the two major sources of energy loss, conduction and switching, reducing the environmental impact of daily-use equipment. a full analysis on the power losses of the complete system in reported in section 4: power losses and dissipation . 2.2 freewheeling diodes turbo 2 ultrafast high voltage diodes have been adequately selected for the sllimm-nano family and carefully tuned to achieve the best t rr /vf trade-off and softness as freewheeling diodes in order to further improve the total performance of the inverter and significantly reduce the electromagnetic interference (emi) in the motor control applications which are quite sensitive to this phenomena. 2.3 high voltage gate drivers the sllimm-nano is equipped with a versatile high voltage gate driver ic (hvic), designed using bcd offline (bipolar, cmos, and dmos) technology (see figure 8 ) and particularly suited to field oriented control (foc) motor driving applications, able to provide all the functions and current capability necessary for high-side and low-side igbt driving. this driver can be used in all applications where high voltage shifted control is necessary and it includes a patented internal circuitry which replaces the external bootstrap diode.
electrical characteristics and functions AN4043 16/60 doc id 022726 rev 2 figure 8. high voltage gate drive die image each high voltage gate driver chip controls two igbts in half bridge topology, offering basic functions such as dead time, interlocking, integrated bootstrap diode, and also advanced features such as smart shutdown (patented), fault comparator, and a dedicated high performance op amp for advanced current sensing. a schematic summary of the features by device are listed in ta bl e 1 . in this application note the main characteristics of a high voltage gate drive related to the sllimm-nano are discussed. for a greater understanding, please refer to the an2738 application note.
AN4043 electrical characteristics and functions doc id 022726 rev 2 17/60 2.3.1 logic inputs the high voltage gate driver ic has two logic inputs, hin and lin, to separately control the high-side and low-side outputs, hvg and lvg. please refer to ta b l e 1 for the input signal logics by device. in order to prevent any cross conduction between high-side and low-side igbt, a safety time (dead time) is introduced (see section 2.3.4: dead time and interlocking function management for further details). all the logic inputs are provided with hysteresis (~1 v) for low noise sensitivity and are ttl/cmos 3.3 v compatible. thanks to this low voltage interface logic compatibility, the sllimm-nano can be used with any kind of high performance controller, such as microcontrollers, dsps or fpgas. as shown in the block diagrams of figure 10 and figure 11 , the logic inputs have internal pull-down (or pull-up) resistors in order to set a proper logic level in the case of interruption in the logic lines. if logic inputs are left floating, the gate driver outputs lvg and hvg are set to low level. this simplifies the interface circuit by eliminating the six external resistors, therefore, saving cost, board space and number of components. figure 9. high voltage gate driver block diagram !-v 78 &'6'%6+10 3 1 9 %227 287 9 5() &,1 +9,& 9 iurp/9* 89 ghwhfwlrq iurp p & iurp p & iurpwr p & 6'2' /,1 +,1 9 && *1' '7 23 287 6pduw vkxw grzq 9 9 9 && 9 && 'hdg wlph wr$'& 9 && 9 && /rjlf 6krrw wkurxjk suhyhqwlrq 6kxwgrzq odwfk /hyho vkliwhu 89 ghwhfwlrq 6 5 )ordwlqjvwuxfwxuh /9* gulyhu +9* gulyhu %rrwvwudsgulyhu %rrwvwudsgulyhu & %227 9 %ldv +9* /9 * %227 6//,00qdqr wrprwru 5 6+817 23 23 5 6) & 6) &3 89: 9 %ldv & ') 5 ') 9 && wr'&olqn 5 6' & 6' &rps 2sdps
electrical characteristics and functions AN4043 18/60 doc id 022726 rev 2 the typical values of the integrated pull-up/down resistors are shown in ta bl e 6 : figure 10. logic input configuration for the stgipn3h60a !-v +9,& 6//,00qdqr 3 1 9 %227 9 && 287 /,1 +,1 +ljkvlgh oh yho vkliwlqj gul yhu /rzvlgh gul yhu 89ghwhfwlrq 89ghwhfwlrq /rjlf 6kr rwwkurxjk suh yhqwlrq %rrwvwudsgulyhu figure 11. logic input configuration for the stgipn3h60 !-v 3 1 9 %227 9 && 287 +,1 +ljkvlgh oh yho vkliwlqj gul yhu /rzvlgh gul yhu 89ghwhfwlrq 89ghwhfwlrq /rjlf 6kr rwwkurxjk suhyhqwlrq 6kx wgrzq /,1 /,1 6' 6pduw6' 9 5() &,1 %rrwvwudsgulyhu +9,& 6//,00qdqr 9
AN4043 electrical characteristics and functions doc id 022726 rev 2 19/60 2.3.2 high voltage level shift the built-in high voltage level shift allows direct connection between the low voltage control inputs and the high voltage power half bridge in any power application up to 600 v. it is obtained thanks to the bcd offline technology which integrates, in the same die bipolar devices, low and medium voltage cmos for analog and logic circuitry and high voltage dmos transistors with a breakdown voltage in excess of 600 v. this key feature eliminates the need for external optocouplers, resulting in significant savings regarding component count and power losses. other advantages are high-frequency operation and short input-to- output delays. 2.3.3 undervoltage lockout the sllimm-nano supply voltage v cc is continuously monitored by an undervoltage lockout (uvlo) circuitry which turns off the gate driver outputs when the supply voltage goes below the v cc_thoff threshold specified on the datasheet, and turns on the ic when the supply voltage goes above the v cc_thon voltage. a hysteresis of about 1.5 v is provided for noise rejection purposes. the high voltage floating supply vboot is also provided with a similar undervoltage lockout circuitry. when the driver is in uvlo condition, both gate driver outputs are set to low level, setting the half bridge power stage output to high impedance. the timing chart of undervoltage lockout, plotted in figure 12 , is based on the following steps: t1: when the v cc supply voltage raises the v cc_thon threshold, the gate driver starts to work after the next input signal hin/lin is on. the circuit state becomes reset t2: input signal hin/lin is on and the igbt is turned on t3: when the v cc supply voltage goes below the v cc_thoff threshold, the uvlo event is detected. the igbt is turned off in spite of input signal hin/lin. the state of the circuit is now set t4: the gate driver re-starts once the v cc supply voltage again raises the v cc_thon threshold t5: input signal hin/lin is on and the igbt is turned on again. table 6. integrated pull-up/down resistor values input pin pn input pin logic internal pull-up internal pull-down high-side gate driving hin u , hin v , hin w stgipn3h60a active high 500 k low-side gate driving lin u , lin v , lin w stgipn3h60a active high 500 k high-side gate driving hin u , hin v , hin w stgipn3h60 active high 85 k low-side gate driving lin u , lin v , lin w stgipn3h60 active low 720 k sd / od shutdown stgipn3h60 active low 125 k
electrical characteristics and functions AN4043 20/60 doc id 022726 rev 2 figure 12. timing chart of undervoltage lockout function 2.3.4 dead time and inte rlocking function management in order to prevent any possible cross-conduction between high-side and low-side igbts, the sllimm-nano provides both the dead time and the interlocking function. the interlocking function is a logic operation which sets both the outputs to low level when the inputs are simultaneously active. the dead time function is a safety time introduced by the device between the falling edge transition of one driver output and the rising edge of the other output. if the rising edge set externally by the user occurs before the end of this dead time, it is ignored and results as delayed until the end of the dead time. the dead time is internally set at 320 ns as the typical value of the stgipn3h60a. !-v 7lph w w w z^d &lufxlwvwdwh w ^d z^d s z?zke w s z?zk&& , & 9 && +,1/,1 table 7. interlocking function truth table of the stgipn3h60a condition logic input (v i ) outputs lin hin lvg hvg interlocking half bridge tri-state hhl l 0 ?logic state? half bridge tri-state llll 1 ?logic state? low-side direct driving hlhl 1 ?logic state? high-side direct driving lhlh
AN4043 electrical characteristics and functions doc id 022726 rev 2 21/60 note: x: not important. the dead time is internally set at 180 ns as typical value. in figure 13 the details of dead time and interlocking function management of the stgipn3h60 is described. table 8. interlocking function truth table of the stgipn3h60 condition logic input (v i ) outputs sd lin hin lvg hvg shutdown enable half bridge tri-state lxxll interlocking half bridge tri-state hlhll 0 ?logic state? half bridge tri-state hhl l l 1 ?logic state? low-side direct driving hllhl 1 ?logic state? high-side direct driving hhhlh
electrical characteristics and functions AN4043 22/60 doc id 022726 rev 2 2.3.5 comparators for fault sensing the sllimm-nano stgipn3h60 integrates one comparator intended for advanced fault protection, such as overcurrent, overtemperature or any other type of fault measurable via a voltage signal. the comparator has an internal reference voltage v ref , specified in the datasheet, on its inverting input (see figure 9 ), while the non-inverting input is available on the c in pin. the comparator input can be connected to an external shunt resistor, in order to implement a simple overcurrent or short-circuit detection function, as discussed in detail in section 2.3.6: short-circuit protection and smart shutdown function . figure 13. timing chart of dead time function lin hin lvg hvg lin hin lvg hvg lin hin lvg hvg lin hin lvg hvg dt lh dt hl dt lh dt hl dt lh dt hl dt lh dt hl gate driver outputs off (half-bridge tri-state) interlocking interlocking control signal edges overlapped: interlocking + dead time control signals edges synchronous (*): dead time control signals edges not overlapped, but inside the dead time: dead time control signals edges not overlapped, outside the dead time: direct driving (*) hin and lin can be connected together and driven by just one control signal interlocking interlocking g g gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) am10496v1
AN4043 electrical characteristics and functions doc id 022726 rev 2 23/60 2.3.6 short-circuit protection and smart shutdown function the fully featured version of the sllimm-nano (stgipn3h60) is able to monitor the output current and provide protection against overcurrent and short-circuit conditions in a very short time (comparator triggering to high/low-side driver turn-off propagation delay t isd = 200 ns), thanks to the smart shutdown function. this feature is based on an innovative patented circuitry which provides an intelligent fault management operation and greatly reduces the protection intervention delay independently on the protection time duration which can be set as desired by the device user. as already mentioned in section 2.3.5: comparators for fault sensing and as shown in figure 9 , the comparator input can be connected to an external shunt resistor, r shunt , in order to implement a simple overcurrent detection function. an rc filter network (r sf and c sf ) is necessary to prevent erroneous operation of the protection. the output signal of the comparator is fed to an integrated mosfet with the open drain available on the sd / od pin, shared with the sd input. when the comparator triggers, the device is set in shutdown state and all its outputs are set to low level, leaving the half bridge in tri-state. in common overcurrent protection architectures, the comparator output is usually connected to the sd input and an external rc network (r sd and c sd ) is connected to this sd / od line in order to provide a mono-stable circuit which implements a protection time when a fault condition occurs. contrary to common fault detection systems, the new smart shutdown structure allows an immediate turn-off of the output gate driver in the case of fault, without waiting for the external capacitor to be discharged. this strategy minimizes the propagation delay between the fault detection event and the actual outputs switch-off. in fact, the time delay between the fault and outputs disabling is not dependent on the rc value of the external sd circuitry but, thanks to the new architecture, has a preferential path internally in the driver. then the device immediately turns off the driver outputs and latches the turn-on of the open drain switch, until the sd signal has reached its lower threshold. after the sd signal goes below the lower threshold, the open drain is switched off (see figure 15 ). the smart shutdown system provides the possibility to increase the value of the external rc network across the sd pin (sized to fix the disable time generated after the fault event) as much as desired by the user without compromising the intervention time delay of the sllimm-nano protection. a block diagram of the smart shutdown architecture is depicted in figure 14 .
electrical characteristics and functions AN4043 24/60 doc id 022726 rev 2 figure 14. smart shutdown equivalent circuitry in normal operation the outputs follow the commands received from the respective input signals. when a fault detection event occurs, the fault signal (fsd) is set to high by the fault detection circuit output and the ff receives a set input signal. consequently, the ff outputs set the sllimm-nano output signals to low level and, at the same time, turn on the open drain mosfet which works as active pull-down for the sd signal. note that the gate driver outputs stay at low level until the sd pin has experienced both a falling edge and a rising edge, although the fault signal may be returned to low level immediately after the fault sensing. in fact, even if the ff is reset by the falling edge of the sd input, the sd signal also works as enable for the outputs, thanks to the two and ports. moreover, once the internal open drain transistor has been activated, due to the latch, it cannot be turned off until the sd pin voltage reaches the low logic level. note that, since the ff is set dominant, oscillations of the sd pin are avoided if the fault signal remains steady at a high level. 2.3.7 timing chart of short-circuit pr otection and smart shutdown function with reference to figure 15 , the short-circuit protection is based on the following steps: t1: when the output current is lower than the max. allowed level, the sllimm-nano is working in normal operation t2: when the output current reaches the max. allowed level (i sc ), the overcurrent/short- circuit event is detected and the protection is activated. the voltage across the shunt resistor, and then on the c in pin, exceeds the v ref value, the comparator triggers, setting the device in shutdown state and both its outputs are set to low level leading the half bridge in tri-state. the smart shutdown switches off the igbt gate (hvg, lvg) through a preferential path (200 ns as typical internal delay time) and, at the same time, it switches on the m1 internal mosfet. the sd signal starts the discharge phase and its value drops with a time constant a . the time constant a value is given by: !-v 9 5() +9,& 6(7grplqdqw)) /9 * +9* 6//,00qdqr &3 &rps )6' +,1 /,1 6' 9 %ldv ([fhswiru67*,36.$ 46 4 5
AN4043 electrical characteristics and functions doc id 022726 rev 2 25/60 equation 2 t3: the sd signal reaches the lower threshold v sd_l_thr and the control unit switches off the input hin and lin. the smart shutdown is disabled (m1 off) and sd can rise up with a time constant b , given by: equation 3 t4: when the sd signal reaches the upper threshold v sd_h_thr , the system is re- enabled. 2.3.8 current sensing s hunt resistor selection as previously discussed, the shunt resistors r shunt externally connected between the n pin and ground (see figure 9 ) are used to realize the overcurrent detection. when the output current exceeds the short-circuit reference level (i sc ), the c in signal overtakes the v ref value and the short-circuit protection is active. for a reliable and stable operation the current sensing resistor should be a high quality, low tolerance non-inductive type. in fact, stray inductance in the circuit, which includes the layout, the rc filter, and also the shunt resistor, must be minimized in order to avoid undesired short-circuit detection. for these reasons, the shunt resistor and the filtering components must be placed as close as possible to the sllimm-nano pins, for additional suggestions refer to section 5.1: layout suggestions . () sd sd od _ on a c r // r ? = sd sd b c r ? = figure 15. timing chart of smart shutdown function !-v 7lph 7lph&rqvwdqwv s z& / ^ w w w 9 vgb+b7+5 9 vgb/b7+5 w w w $ 5 21b2' 5 6' & 6' w % 5 6' & 6' 6'glvfkdujhwlph 6'uhfkdujhwlph +9*/9* 9 6+817 aa9 &,1 , & 6' 0 w 5&flufxlwwlph frqvwdqw +,1/,1 iurpwr p & 6'2' 0 6pduw vkxw grzq 9 %ldv 5 6' & 6' 6//,00qdqr 5 21b2' 6kxwgrzqflufxlw
electrical characteristics and functions AN4043 26/60 doc id 022726 rev 2 the value of the current sense resistor can be calculated by following different guidelines, functions of the design specifications, or requirements. a common criterion is presented here based on the following steps: defining of the overcurrent threshold value (i oc_th ). for example, it can be fixed considering the igbt typical working current in the application and adding 20-30% as overcurrent. calculation of the shunt resistor value according to the conditioning network. an example of the conditioning network is shown in figure 19 . further details can be found in the user manuals listed (see references 5 and references 6). selection of the closest shunt resistor commercial value. calculation of the power rating of the shunt resistor, taking into account that this parameter is strongly temperature dependent. therefore, the power derating ratio of the shunt resistor, p(t)%, shown in the manufacturer's datasheet, must be considered in the calculation as follows: equation 4 where i rms is the igbt rms working current. for a proper selection of the shunt resistor, a safety margin of at least 30% is recommended on the calculated power rating. 2.3.9 rc filter network selection two options of shunt (1- or 3-shunt) resistor circuit can be adopted in order to implement different control techniques and short-circuit protection, as shown in figure 16 . an rc filter network is required to prevent undesired short-circuit operation due to the noise on the shunt resistor. )% t ( p i r ) t ( p 2 rms shunt shunt ? = figure 16. examples of sc protection circuit !-v 6//,00qdqr & 6) 5 6) 5 6+817 &,1 1: 18 19 6//,00qdqr & 6) 5 6) 5 6+817 &,1 1: 18 19 5 6+817b8 5 6+817b: 5 6+817b9 vkxqwuhvlvwruflufxlw vkxqwuhvlvwruvflufxlw
AN4043 electrical characteristics and functions doc id 022726 rev 2 27/60 both solutions allow to detect the total current in all three phases of the inverter. the filter is based on the r sf and c sf network and its time constant is given by: equation 5 in addition to the rc time constant, the turn-off propagation delay of the gate driver, t isd (specified in the datasheet) and the igbt turn-off time (in the range of tens of ns), must be considered in the total delay time (t to t a l ), which is the time necessary to completely switch off the igbt once the short-circuit event is detected. therefore, the t to t a l is calculated as follows: equation 6 and the t sf is recommended to be set in the range of 1~2 s. in the case of a 3-shunt resistor circuit, a specific control technique can be implemented by using the three shunt resistors (r shunt_u , r shunt_v and r shunt_w ) able to monitor each phase current. an example of a short-circuit event is shown in figure 17 , where it is possible to note the very fast protection, thanks to the smart shutdown function, against fault events. the main steps are: t1: collector current ic starts to rise. sc event is not detected yet due to the rc network on the c in pin. t2: voltage on v cin reaches the v ref . sc event is detected and the smart shutdown starts to turn off the sllimm-nano. t3: the sd in activated. t4: the sllimm-nano is definitively turned off in 580 ns (including the t d(off) time of igbt) from sc detection. finally, the total disable time is t4-t2 and the total sc action time is t4-t1. sf sf sf c r t ? = off isd sf total t t t t + + =
electrical characteristics and functions AN4043 28/60 doc id 022726 rev 2 2.3.10 op amps for advanced current sensing the fully featured version of the sllimm-nano (stgipn3h60) integrates also one operational amplifier optimized for field oriented control (foc) applications. in a typical foc application the currents in the three half bridges are sensed using a shunt resistor. the analog current information is transformed into a discontinuous sense voltage signal, having the same frequency as the pwm signal driving the bridge. the sense voltage is a bipolar analog signal, whose sign depends on the direction of the current (see figure 18 ): figure 17. example of sc event !-v &,1 +,1 , & $'ly &,1 9'ly +,1 9'ly w qv'ly , & 7lph w w w qv s z& 6' 9'ly 6' w 9 vgb+b7+5 6//,00qdqr 3 1 89: 5 6+817 wrprwru &,1 , & 6&hyhqwrqwkh orzvlgh,*%7 wr'&olqn ([dpsohri6&hyhqw +,1 +9,&
AN4043 electrical characteristics and functions doc id 022726 rev 2 29/60 the sense voltage signals must be provided to an a-d converter. they are usually shifted and amplified by dedicated op amps in order to exploit the full range of the a-d converter. the typical scheme and principle waveforms are shown in figure 19 : figure 18. 3-phase system 3-phase driver sinusoidal vector control sensing: discontinuous voltage at f pwm frequency 9 6 9 6 9 6 discontinuous voltage at f pwm frequency power stage skdvh prwru i phase am09338v1 figure 19. general advanced current sense scheme and waveforms !-v 9 vhqvh +doieulgjh fxuuhqwvhqvlqj 9r owdjh vkliwlqj riwkh9 vhqvh 6hqvhyrowdjhvljqdo 6kliwhgdqgfhqwhuhg vljqdo $psolilhgvljqdo )lowhuhgvljqdo 9rowdjhjdlq dqgilowhulqj 5 287 uhtxluhgwr pdnhwkh rsdpsvwdeoh & 287 uhtxluhge\wkh$'& iruvdpsolqjsxusrvh 9 5() 5 6+817 23 & 287 & 5 5 5 5 23 5 287 2sdps 5 wrprwru wr'&olqn wr$'&
electrical characteristics and functions AN4043 30/60 doc id 022726 rev 2 adcs used in vector control applications have a typical full scale range (fsr) of about 3.3 v. the sense signals must be shifted and centered on fsr/2 voltage (about 1.65 v) and amplified with a gain which provides the matching between the maximum value of the sensed signal and the fsr of the adc. some typical examples of sense network sizing can be found in the user manuals listed (see references 5 and references 6 ). 2.3.11 bootstrap circuit in the 3-phase inverter the emitters of the low-side igbts are connected to the negative dc bus (v dc- ) as common reference ground, which allows all low-side gate drivers to share the same power supply, while, the emitter of high-side igbts is alternately connected to the positive (v dc+ ) and negative (v dc- ) dc bus during the running conditions. a bootstrap method is a simple and cheap solution to supply the high voltage section. this function is normally accomplished by a high voltage fast recovery diode. the sllimm-nano family includes a patented integrated structure that replaces the external diode. it is realized with a high voltage dmos driven synchronously with the low-side driver (lvg) and a diode in series. an internal charge pump provides the dmos driving voltage. the operation of the bootstrap circuit is shown in figure 20 . the floating supply capacitor c boot is charged, from the v cc supply, when the v out voltage is lower than the v cc voltage (e.g. low-side igbt is on), through the bootstrap diode and the dmos path with reference to the ?bootstrap charge current path?. during the high-side igbt on phase, the bootstrap circuit provides the right gate voltage to properly drive the igbt (see ?bootstrap discharge current path?). this circuit is iterated for all the three half bridges. figure 20. bootstrap circuit the value of the c boot capacitor should be calculated according to the application condition and must take the following into account: voltage across c boot must be maintained at a value higher than the undervoltage lockout level for the ic driver. this enables the high-side igbt to work with a correct gate voltage (lower dissipation and better overall performances). please consider that if !-v /hjhqg & %227 287 +9* 9 errw /9* 3 1 89: '026 9 errw 9 && *1' /,1 287 9 && 6//,00qdqr errwvwuds glrgh fkdujh sxps +9,& %rrwvwuds fkdujh fxuuhqwsdwk %rrwvwuds glvfkdujh fxuuhqwsdwk
AN4043 electrical characteristics and functions doc id 022726 rev 2 31/60 a voltage below the uvlo threshold is applied on the bootstrap channel, the ic disables itself (no output) without any fault signal. the voltage across c boot is affected by different components such as drop across the integrated bootstrap structure, drop across the low-side igbt, and others. when the high-side igbt is on, the c boot capacitor discharges mainly to provide the right igbt gate charge but other phenomena must be considered such as leakage currents, quiescent current, etc. 2.3.12 bootstrap capacitor selection a simple method to properly size the bootstrap capacitor considers only the amount of charge that is needed when the high voltage side of the driver is floating and the igbt gate is driven once. this approach does not take into account either the duty cycle of the pwm, or the fundamental frequency of the current. observations on pwm duty cycle, the kind of modulation (6-step, 12-step and sine-wave) must be considered with their own peculiarity to achieve the best bootstrap circuit sizing. during the bootstrap capacitor charging phase, the low-side igbt is on and the voltage across c boot (v cboot ) can be calculated as follows: equation 7 where: v cc : supply voltage of gate driver. v f : bootstrap diode forward voltage drop. v ce(sat)max : maximum emitter collector voltage drop of low-side igbt. v rds(on) : dmos voltage drop. the dimension of the bootstrap capacitance c boot value is based on the minimum voltage drop ( v cboot ) to guarantee when the high-side igbt is on, and must be: equation 8 under the condition: equation 9 where: v ge(min) : minimum gate emitter voltage of high-side igbt. v bs_thon : bootstrap turn-on undervoltage threshold (maximum value, see datasheet). considering the factors contributing to v cboot decreasing, the total charge supplied by the bootstrap capacitor (during high-side on phase) is: max ) sat ( ce ) on ( rds f cc cboot v v v v v ? ? ? = max ) sat ( ce (min) ge ) on ( rds f cc cboot v v v v v v ? ? ? ? = thon _ bs (min) cboot v v >
electrical characteristics and functions AN4043 32/60 doc id 022726 rev 2 equation 10 where: q gate : total igbt gate charge. i lkge : igbt gate emitter leakage current. i qbo : bootstrap circuit quiescent current. i lk : bootstrap circuit leakage current. i lkdiode : bootstrap diode leakage current. i lkcap : bootstrap capacitor leakage current (relevant when using an electrolytic capacitor but can be ignored if other types of capacitors are used). t hon : high-side on time. q ls : charge required by the internal level shifters. finally, the minimum size of the bootstrap capacitor is: equation 11 for an easier selection of bootstrap capacitor, figure 21 shows the behavior of c boot (calculated) versus switching frequency (f sw ), with different values of v cboot , corresponding to equation 11 equation 11 for a continuous sinusoidal modulation and a duty cycle = 50%. figure 21. bootstrap capacitor vs. switching frequency () ls hon ap lkc lkdiode lk qbo lkge ga te to t q t i i i i i q q + ? + + + + + = cboot tot boot v q c = am11 8 14v1 0 1 2 3 4 5 0 5 10 15 20 f sw (khz) c boot calculated (f) stgipn3h60a stgipn3h60 = 50% v cb oot =0.1v v cboot =0.3v v cboot =0.5v
AN4043 electrical characteristics and functions doc id 022726 rev 2 33/60 considering the limit cases during the pwm control and further leakages and dispersions in the board layout, the capacitance value to use in the bootstrap circuit must be selected two or three times higher than the c boot calculated in the graph of figure 21 . the bootstrap capacitor should be with a low esr value for a good local decoupling, therefore, in case an electrolytic capacitor is used, one parallel ceramic capacitor placed directly on the sllimm- nano pins is strictly recommended. 2.3.13 initial bootstra p capacitor charging during the startup phase, the bootstrap capacitor must be charged for a suitable time to complete the initial charging time (t charge ), which is, at least, the time v cboot needs to exceed the turn-on undervoltage threshold v bs_thon , as already stated in equation 9equation 9 . for a normal operation, the voltage across the bootstrap capacitor must never drop down to the turn-off undervoltage threshold v bs_thoff throughout the working conditions. for the period of startup, only the low-side igbt is switched on and, just after this phase, the pwm is run, as shown in the following steps of figure 22 : t1: the bootstrap capacitor starts to charge through the low-side igbt (lvg) t2: the voltage across the bootstrap capacitor (v cboot ) reaches its turn-on undervoltage threshold v bs_thon t3: the bootstrap capacitor is fully charged; this enables the high-side igbt and the c boot capacitor starts to discharge in order to provide the right igbt gate charge. the bootstrap capacitor recharges during the on-state of the low-side igbt (lvg). figure 22. initial bootstrap charging time the initial charging time is given by equation 12 equation 12 and must be, for safety reasons, at least three times longer than the calculated value. !-v 7lph 9 &%227 w /9* 9 && '&%xv9 31 9 %6bwk21 w w +9* 9 %6bwk2))
electrical characteristics and functions AN4043 34/60 doc id 022726 rev 2 equation 12 where is the duty cycle of the pwm signal and r ds(on) is 120 typical value, as shown in the datasheet. a practical example can be done by considering a motor drive application where the pwm switching frequency is 16 khz, with a duty cycle of 50%, and v cboot = 0.1 v (that means, a gate driver supply voltage v cc = 17.5 v). from the graph in figure 21 the bootstrap capacitance is 1.0 f, therefore the c boot can be selected by using a value between 2.0 and 3.0 f. according to the commercial value the bootstrap capacitor can be 2.2 f. from equation 12equation 12 , the initial charging time is: equation 13 for safety reasons, the initial charging time must be at least 8.1 ms. ? ? ? ? ? ? ? ? ? cboot cc ) on ( ds boot charge v v ln * r c t ms 7 . 2 1 . 0 5 . 17 ln 5 . 0 120 10 2 . 2 t 6 charge = ? ? ? ? ? ? ? ? ? ? ? ?
AN4043 package doc id 022726 rev 2 35/60 3 package the ndip is a dual-in-line transfer mold package available in 26-lead version (ndip-26l) able to meet demanding cost and size requirements of consumer appliance inverters. it consists of a copper lead frame with power stage and control stage soldered on it and housed using the transfer molding process. the excellent thermal properties of the copper allows good heat spread and heat transfer, furthermore, the thickness and the layout of the lead frames has been optimized in order to further reduce the thermal resistance. the package pinout has been designed in order to maximize the distance between the high voltage and low voltage pins, by placing the relevant pins on the opposite side of the package. this is mainly useful to keep a safe distance between high voltage and low voltage pins and for an easy pcb layout. finally, thanks to the transfer molding technology and design optimization, the sllimm- nano offers a high power density level in a very compact package while providing good thermal propriety, electrical isolation and overall reliable performance. 3.1 package structure figure 23 contains the images and an internal structure illustration of the ndip-26l package. figure 23. images and internal view of ndip-26l package top view bottom view internal view x = 29.5 mm y 1 = 12.5 mm (body only) y 2 = 22 mm (including leads) z 1 = 3.1 mm (body only) z 2 = 7 mm (including leads) main dimensions x y z s l l i m m - n a n o sllimm-nano ndip-26l igbt fwd hvic
package AN4043 36/60 doc id 022726 rev 2 3.2 package outline and dimensions figure 24. outline drawing of ndip-26l package b1,b3 b,b2 c c1 d e eb1 eb2 e b d1 a3 e1 d2 a1 a4 l a a2 b2 d3 0.075 0.075 am11815v1 8278949_a
AN4043 package doc id 022726 rev 2 37/60 3.3 input and output pins description this paragraph defines the input and output pins of the sllimm-nano. for a more accurate description and layout suggestions, please consult the relevant sections. table 9. outline drawing of ndip-26l package dimension (mm) min. typ. max. a4.4 a1 0.811.2 a2 3 3.1 3.2 a3 1.7 1.8 1.9 a4 5.7 5.9 6.1 b0.53 0.72 b1 0.52 0.6 0.68 b2 0.83 1.02 b3 0.82 0.9 0.98 c0.46 0.59 c1 0.45 0.5 0.55 d 29.05 29.15 29.25 d1 0.5 d2 0.35 d3 29.55 e 12.35 12.45 12.55 e1.71.81.9 e1 2.4 2.5 2.6 eb1 16.1 16.4 16.7 eb2 21.18 21.48 21.78 l 1.24 1.39 1.54
package AN4043 38/60 doc id 022726 rev 2 figure 25. pinout (top view) table 10. input and output pins pin # name description stgipn3h60a stgipn3h60 stgipn3h60a stgipn3h60 1 gnd ground 2nc sd / od not connected shutdown logic input (active low) / open drain (comparator output) 3v cc w low voltage power supply w phase 4hin w high-side logic input for w phase 5lin w lin w low-side logic input for w phase (active high) low-side logic input for w phase (active low) 6nc op + not connected op amp non inverting input 7nc op out not connected op amp output 8nc op - not connected op amp inverting input 9v cc v low voltage power supply v phase 10 hin v high-side logic input for v phase 11 lin v lin v low-side logic input for v phase (active high) low-side logic input for v phase (active low) 12 nc cin not connected comparator input 13 v cc u low voltage power supply u phase 14 hin u high-side logic input for u phase 15 nc sd / od not connected shutdown logic input (active low) / open drain (comparator output) 16 lin u lin u low-side logic input for u phase (active high) low-side logic input for u phase (active low) 17 v bootu bootstrap voltage for u phase
AN4043 package doc id 022726 rev 2 39/60 high-side bias voltage pins /high-side bias voltage reference pins: v bootu -u, v bootv -v, v bootw -w the bootstrap section is designed to realize a simple and efficient floating power supply, in order to provide the gate voltage signal to the high-side igbts the sllimm-nano family integrates the bootstrap diodes. this helps users to save costs, board space, and number of components the advantage of the ability to bootstrap the circuit scheme is that no external power supplies are required for the high-side igbts each bootstrap capacitor is charged from the vcc supply during the on-state of the corresponding low-side igbt to prevent malfunction caused by noise and ripple in supply voltage, a good quality (low esr, low esl) filter capacitor should be mounted close to these pins the value of bootstrap capacitors is strictly related to the application conditions. please consult section 2.3.11: bootstrap circuit for more information. gate driver bias voltage pins: v cc u , v cc v , v cc w control supply pins for the built-in ics to prevent malfunction caused by noise and ripple in the supply voltage, a good quality (low esr, low esl) filter capacitor should be mounted close to these pins. gate drive supply ground pin: gnd ground reference pin for the built-in ics to avoid noise influence, the main power circuit current should not be allowed to flow through this pin (see section 5.1: layout suggestions ). pin # name description stgipn3h60a stgipn3h60 stgipn3h60a stgipn3h60 18 p positive dc input 19 u u phase output 20 n u negative dc input for u phase 21 v bootv bootstrap voltage for v phase 22 v v phase output 23 n v negative dc input for v phase 24 v bootw bootstrap voltage for w phase 25 w w phase output 26 n w negative dc input for w phase table 10. input and output pins (continued)
package AN4043 40/60 doc id 022726 rev 2 signal input pins: hin u , hin v , hin w ; lin u , lin v , lin w ; lin u , lin v , lin w these pins control the operation of the built-in igbts. the signal logic of hin u , hin v , hin w , lin u , lin v , and lin w pins is active high. the igbt associated with each of these pins is turned on when a sufficient logic (higher than a specific threshold) voltage is applied to these pins. the signal logic of lin u , lin v , lin w pins is active low. the igbt associated with each of these pins is turned on when a logic voltage (lower than a specific threshold voltage) is applied to these pins. the wiring of each input should be as short as possible to protect the sllimm-nano against noise influence. rc coupling circuits should be adopted for the prevention of input signal oscillation. suggested values are r =100 and c=1nf. internal comparator non-inverting (only for the stgipn3h60) pin: cin the current sensing shunt resistor, connected on each phase leg, may be used by the internal comparator (pin cin) to detect short-circuit current the shunt resistor should be selected to meet the detection levels matched for the specific application an rc filter (typically ~1 s) should be connected to the cin pin to eliminate noise the connection length between the shunt resistor and cin pin should be minimized if a voltage signal, higher than the specified v ref (see datasheet), is applied to this pin, the sllimm-nano automatically shuts down and the sd / od pin is pulled down (to inform the microcontroller). shutdown / open drain (only for the stgipn3h60) pins: sd / od there are two available pins of sd / od which are exactly the same. they are placed on the opposite ends of the package in order to offer higher flexibility to the pcb layout. it is sufficient to use only one of the two pins for the proper functioning of the device. the sd / od pins work as enable/disable pins. the signal logic of sd / od pins are active low. the sllimm-nano shuts down if a voltage lower than a specific threshold is applied to these pins, leading each half bridge in tri-state. the sd / od status is connected also to the internal comparator status ( section 2.3.6: short-circuit protection and smart shutdown function ). when the comparator triggers, the sd / od pin is pulled down acting as a fault pin. the sd / od, when pulled down by the comparator, are open drain configured. the sd / od voltage should be pulled up to the 3.3 v or 5 v logic power supply through a pull- up resistor. integrated operational amplifier (only for the stgipn3h60) pins: op+, op-, op out the op amp is completely uncommitted the op amp performance is optimized for advanced control technique (foc) thanks to the integrated op amp, it is possible to realize a compact and efficient board layout, minimizing the required bom list.
AN4043 package doc id 022726 rev 2 41/60 positive dc-link pin: p this is a dc-link positive power supply pin of the inverter and it is internally connected to the collectors of the high-side igbts to suppress the surge voltage caused by the dc-link wiring or pcb pattern inductance, connect a smoothing filter capacitor close to the p pin. generally a 0.1 or 0.22 f high frequency, high voltage non-inductive capacitor is recommended. negative dc-link pins: n u , n v , n w these are the dc-link negative power supply pins (power ground) of the inverter these pins are connected to the low-side igbt emitters of each phase the power ground of the application should be separated from the logic ground of the system and they should be reconnected at one specific point (star connection). inverter power output pins: u, v, w inverter output pins for connecting to the inverter load (e.g. motor).
power losses and dissipation AN4043 42/60 doc id 022726 rev 2 4 power losses and dissipation the total power losses in an inverter are comprised of conduction losses, switching losses, and off-state losses and they are essentially generated by the power devices of the inverter stage, such as the igbts and the freewheeling diodes. the conduction losses (p cond ) are the on-state losses during the conduction phase. the switching losses (p sw ) are the dynamic losses encountered during turn-on and turn-off. the off-state losses, due to the blocking voltage and leakage current, can be neglected. finally, the total power losses are given by: equation 14 figure 26 shows a typical waveform of an inductive hard switching application such as a motor drive, where the major sources of power losses are specified. 4.1 conduction power losses the conduction losses are caused by igbt and freewheeling diode forward voltage drop at rated current. they can be calculated using a linear approximation of the forward characteristics for both the igbt and diode, having a series connection of dc voltage source representing the threshold voltage, v to for igbt, (and v fo for diode) and a collector emitter on-state resistance, r ce , (and anode cathode on-state resistance, r ak ), as shown in figure 27 . sw cond tot p p p + figure 26. typical igbt power losses am09 3 57v1 v ce i c 10% i c 10% v ce 10% v ce 10% i c e sw(on) e sw(off) v ce(sat) t c(on) t c(off) conduction
AN4043 power losses and dissipation doc id 022726 rev 2 43/60 both forward characteristics are temperature dependent, and so must be considered under a specified temperature. the linear approximations can be translated for igbt in the following equation: equation 15 and, for freewheeling diode: equation 16 the conduction losses of igbt and diode can be derived as the time integral of the product of conduction current and voltage across the devices, as follows: equation 17 equation 18 where t is the fundamental period. the different utilization mode of the sllimm-nano, modulation technique, and working conditions make the power losses very difficult to estimate, it is therefore necessary to fix some starting points. figure 27. igbt and diode approximation of the output characteristics v to r ce = v ce / i c i c v ce v to r ce = v ce / i c i c v ce v fo r ak = v fm / i fm i fm v fm v fo r ak = v fm / i fm i fm v fm am09345v1 c ce to c ce i r v ) (i v ? + = fm ak fo fm fm i r v ) (i v ? + = ? ? ? ? ? ? ? + ? = ? = t 0 2 c ce c to t 0 c ce cond_igbt dt (t) i r (t) i v t 1 (t)dt i v t 1 p ? ? ? ? ? ? ? + ? = ? = t 0 2 f ak f fo t 0 f f cond_diode dt (t) i r (t) i v t 1 (t)dt i v t 1 p
power losses and dissipation AN4043 44/60 doc id 022726 rev 2 assuming that: 1. the application is a variable voltage variable frequency (vvvf) inverter based on sinusoidal pwm technique. 2. the switching frequency is high and therefore the output currents are sinusoidal. 3. the load is ideal inductive. under these conditions, the output inverter current is given by: equation 19 where ? is the current peak, stands for t and is the phase angle between output voltage and current. the conduction power losses can be obtained as: equation 20 equation 21 where is the duty cycle for this pwm technique and is given by: equation 22 and m a is the pwm amplitude modulation index. finally, solving equation 20equation 20 and equation 21equation 21 , we have: equation 23 equation 24 () = - cos i ? i () () ? + ? = + + ? + + ? d - cos 2 i ? r d - cos 2 i ? v p 2 2 2 2 2 2 ce to cond_igbt ()() () () + + ? + + ? ? + ? = 2 2 2 2 d - cos 1 2 i ? r d - cos 1 2 i ? v p 2 2 ak fo cond_diode 2 cos m 1 a ? + = ? ? ? ? ? ? ? ? ? + ? + ? ? ? ? ? ? ? ? ? + ? = 3 cos m 8 1 2 i ? r 8 cos m 2 1 i ? v p a 2 ce a to cond_igbt ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? = 3 cos m 8 1 2 i ? r 8 cos m 2 1 i ? v p a 2 ak a fo cond_diode
AN4043 power losses and dissipation doc id 022726 rev 2 45/60 and therefore, the conduction power losses of one device (igbt and diode) are: equation 25 of course, the total conduction losses per inverter are six times this value. 4.2 switching power losses the switching loss is the power consumption during the turn-on and turn-off transients. as already shown in figure 26 , it is given by the pulse of power dissipated during the turn-on (t on ) and turn-off (t off ). experimentally, it can be calculated by the time integral of product of the collector current and collector-emitter voltage for the switching period. however, the dynamic performance is strictly related to many parameters such as voltage, current and temperature, so it is necessary to use the same assumptions of conduction power losses ( section 4.1: conduction power losses ) to simplify the calculations. under these conditions, the switching energy losses are given by: equation 26 equation 27 where on and off are the maximum values taken at t jmax and ? c , stands for t and is the phase angle between output voltage and current. finally, the switching power losses per device depend on the switching frequency (f sw ) and they are calculated as follows: equation 28 where e igbt and e diode are the total switching energy for the igbt and the freewheeling diode, respectively. also in this case, the total switching losses per inverter are six times this value. figure 28 shows the real turn-on and turn-off waveforms of the stgipn3h60 under the following conditions: v pn = 300 v, i c = 0.5 a, t j = 100 c with inductive load on full bridge topology, taken on the low-side igbt. the green plots represent instantaneous power as a result of ic (in red) and v ce (in yellow) waveforms multiplication, during the switching transitions. the areas under these plots are the switching energies computed by graphic integration thanks to the digital oscilloscope. cond_diode cond_igbt cond p p p + = () = - cos e ? ) ( e on on () = - cos e ? ) ( e of f off + + ? + = ? + = 2 2 - sw diode igbt sw diode igbt sw f ) e e ( d f ) e e ( 2 1 p
power losses and dissipation AN4043 46/60 doc id 022726 rev 2 4.3 thermal impedance overview during operation, power losses generate heat which elevates the temperature in the semiconductor junctions contained in the sllimm-nano, limiting its performance and lifetime. to ensure safe and reliable operation, the junction temperature of power devices must be kept below the limits defined in the datasheet, therefore, the generated heat must be conducted away from the power chips and into the environment using an adequate cooling system. the sllimm-nano was designed to drive electric motors up to 100 w without any heatsink. therefore, the thermal aspect of the system is one of the key factors in designing high efficiency and high reliability equipment. in this environment the package and its thermal resistance play a fundamental role. thermal resistance quantifies the capability of a given thermal path to transfer heat in steady-state and it is generically given as the ratio between the temperature increase above the reference and the relevant power flow: equation 29 the thermal resistance specified in the datasheet is the junction-ambient r th(j-a) which is commonly used with natural and forced convection air cooled systems and it is defined as the difference in temperature between junction and ambient reference divided by the power dissipation per device: equation 30 figure 28. typical switching waveforms of the stgipn3h60 v ce e on =23.5 j(*) i c t on = 270ns v lin = 2v/div i c = 500ma/div v ce = 100v/div t = 100ns/div v lin turn on stgipn3h60 low side tj=100 c turn off stgipn3h60 low side tj=100 c t off = 905ns (*) e on and e off are the areas under the red plots e = (v ce i c ) dt v ce e off =5.1 j(*) i c v lin v lin = 2v/div i c = 200ma/div v ce = 100v/div t = 200ns/div am11816v1 p t r th = d amb j a) th(j- p t t r ? =
AN4043 power losses and dissipation doc id 022726 rev 2 47/60 figure 29 shows an equivalent circuit of the thermal resistance between junction and ambient r th(j-a) . figure 29. r th(j-a) equivalent thermal circuit as the power loss p tot is cyclic, also the transient thermal impedance must be considered. it is defined as the ratio between the time dependent temperature increase above the reference, t(t), and the relevant heat flow: equation 31 contrary to that already seen regarding the thermal resistance, the thermal impedance is typically represented by an rc equivalent circuit. for pulsed power loss, the thermal capacitance effect delays the rise in junction temperature and therefore the advantage of this behavior is the short-term overload capability of the sllimm-nano. for example, figure 30 shows thermal impedance from a junction to ambient curve for a single igbt of the sllimm-nano. figure 30. thermal impedance z th(j-a) curve for a single igbt am11817v1 p ) t ( t ) t ( z th = am11 8 1 8 v1 sllimm-nano z th(j-a) 0 10 20 30 40 50 60 1.e-05 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 time (sec) z th(j-a) (c/w)
power losses and dissipation AN4043 48/60 doc id 022726 rev 2 more generally, in the case of the device, power is time dependent too. the device temperature can be calculated by using the convolution integral method applied to equation 31equation 31 , as follows: equation 32 an alternative method, very useful for the simulator tools, is the transient thermal impedance model, which provides a simple method to estimate the junction temperature rise under a transient condition. by using the thermo-electrical analogy, the transient thermal impedance z th(t) can be transformed into an electrical equivalent rc network. the number of rc sections increases the model details, therefore a twelfth order model, for z th(j-a) , based on the cauer and foster networks, has been used in order to improve the accuracy of both models. figure 31 and figure 32 show the general cauer and foster rc equivalent circuit used for the thermal impedance model. figure 31. cauer rc equivalent circuit figure 32. foster rc equivalent circuit temperatures inside the electrical rc network represent voltages, power flows represent currents, electrical resistances and capacitances represent thermal resistances and capacitances respectively. the case temperature is represented with a dc voltage source and it can be interpreted as the initial junction temperature. transient thermal impedance models are derived by curve fitting an equation to the measured data. values for the individual resistors and capacitors are the variables from that equation and are defined in ta b l e 1 1 , for both z th(j-a) cauer and foster thermal impedance models. ? ? = d ) ( p ) t ( z ) t ( t t 0 th am11 8 19v1 7 m 3 wrw w c1 c2 c3 cn r1 r2 r3 rn 7 dpe = wk w am11 8 20v1 r1 r2 r3 rn 7 m 3 wrw w c1 c2 c3 cn 7 dpe = wk w
AN4043 power losses and dissipation doc id 022726 rev 2 49/60 4.4 power loss calculation example as a result of power loss calculation and thermal aspects, fully treated in the previous sections, it is possible to simulate the maximum i c(rms) current versus switching frequency curves for a vvvf inverter using a 3-phase sinusoidal pwm and a six-step 120 switching modulation to synthesize sinusoidal output currents. the curves graphed in figure 33 represent the maximum current managed by the sllimm- nano in safety conditions, when the junction temperature rises to the maximum junction temperature of 150 c for three ambient temperatures (25, 50 and 75 c), which is a typical operating condition to guarantee the reliability of the system. these curves, functions of the motor drive typology and control scheme, are simulated under the following conditions: v pn = 300 v, m a = 0.8, cos = 0.6, t j = 150 c, t c = 100 c, f sine = 60 hz, max. value of r th(j-c) , typical v ce(sat) and e tot values. table 11. cauer and foster rc thermal network elements element z th(j-a) cauer network z th(j-a) foster network r1 (c/w) 8.96e-01 1.81e-01 r2 (c/w) 9.37e-01 1.71e-01 r3 (c/w) 5.92e-01 8.12e-02 r4 (c/w) 1.37e-02 5.11e-02 r5 (c/w) 2.11e-02 1.86e-01 r6 (c/w) 2.84e+00 6.58e-01 r7 (c/w) 1.26e-01 5.00e-04 r8 (c/w) 4.48e-02 6.95e-02 r9 (c/w) 4.06e-01 5.14e-01 r10 (c/w) 4.93e+00 4.43e+00 r11 (c/w) 9.38e+00 7.90e+00 r12 (c/w) 2.99e+01 3.58e+01 c1 (wsec/c) 6.25e-04 1.55e-01 c2 (wsec/c) 3.81e-03 1.67e-01 c3 (wsec/c) 4.69e-03 1.19e+00 c4 (wsec/c) 2.41e-03 9.09e-01 c5 (wsec/c) 4.39e-03 1.84e-02 c6 (wsec/c) 3.27e-03 1.07e-03 c7 (wsec/c) 1.82e-02 1.77e-03 c8 (wsec/c) 1.32e-02 8.80e-02 c9 (wsec/c) 3.63e-03 1.19e-02 c10 (wsec/c) 6.72e-02 4.74e-02 c11 (wsec/c) 2.75e-02 2.35e-01 c12 (wsec/c) 2.22e+00 1.75e+00
power losses and dissipation AN4043 50/60 doc id 022726 rev 2 figure 33. maximum i c(rms) current vs. f sw simulated curves am11822v1 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 04812162024 i c(rms) (a) f sw (khz) six -step 120 switching ta = 25c ta = 5 0 c v pn = 300 v, modulation index = 0.8, pf = 0.6, t j = 150 c, f sine = 60 hz, duty-cycle=60% ta = 75c 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 04812162024 i c(rms) (a) f sw (khz) 3-phase sinusoidal pwm ta = 25c ta = 5 0 c v pn = 300 v, modulation index = 0.8, pf = 0.6, t j = 150 c, f sine = 60 hz am11821v1 ta = 75c
AN4043 design and mounting guidelines doc id 022726 rev 2 51/60 5 design and mounting guidelines this section introduces the main layout suggestions for an optimized design and major mounting recommendations, to appropriately handle and assemble the sllimm-nano family. 5.1 layout suggestions optimization of pcb layout for high voltage and high switching frequency applications is a critical point. pcb layout is a complex matter as it includes several aspects, such as length and width of track and circuit areas, but also the proper routing of the traces and the optimized reciprocal arrangement of the various system elements in the pcb area. a good layout can help the application to properly function and achieve the expected performance. on the other hand, a pcb without a careful layout can generate emi issues (both induced and perceived by the application), can provide overvoltage spikes due to parasitic inductances along the pcb traces, and can produce higher power loss and even malfunction in the control and sensing stages. the compactness of the sllimm-nano solution, which offers an optimized gate driving network and reduced parasitic elements, allows users to focus only on certain issues, such as the ground issue or noise filter. therefore, in order to avoid all the aforementioned conditions, the following general guidelines and suggestions must be followed in pcb layout for 3-phase applications. 5.1.1 general suggestions pcb traces should be designed to be as short as possible and the area of the circuit (power or signal) should be minimized to avoid the sensitivity of such structures to surrounding noise. ensure a good distance between switching lines with high voltage transitions and the signal line sensitive to electrical noise. specifically, the tracks of each out phase, bringing significant currents and high voltages, should be separated from the logic lines and analog sensing circuit of the op amp and comparator. place the r sense resistors as close as possible to the low-side pins of the sllimm- nano (n u , n v and n w ). parasitic inductance can be minimized by connecting the ground line (also called driver ground) of the sllimm-nano directly to the cold terminal of sense resistors. use of a low inductance type resistor, such as an smd resistor instead of long-lead type resistors, can help to further decrease the parasitic inductance. avoid any ground loop. only a single path must connect two different ground nodes. place each rc filter as close as possible to the sllimm-nano pins in order to increase their efficiency. in order to prevent surge destruction, the wiring between the smoothing capacitor and the p and n pins should be as short as possible. the use of a high frequency, high voltage non-inductive capacitor about 0.1 or 0.22 f between the p and n pins is recommended. fixed voltage tracks, such as gnd or hv lines, can be used to shield the logic and analog lines from the electrical noise produced by the switching lines (e.g. u, v and w). generally it is recommended to connect each half bridge ground in a star configuration and the three r sense very close to each other and to the power ground.
design and mounting guidelines AN4043 52/60 doc id 022726 rev 2 in figure 34 , general suggestions for all sllimm-nano products are summarized. figure 34. general suggestions special attention must be paid to wrong layouts. in figure 35 and figure 36 some common pcb mistakes are shown. figure 35. example 1 on a possible wrong layout v in(vl) v in(vh) to mcu v in(wl) v in(wh) to mcu +15v gnd from power source to moto r shunt resistor + - power gnd (n) v in(ul) v in(uh) shut down to v dd phase current s ignal ground and power ground must be connected at only one point (star connections), avoiding long connections. please ensure a safety distances between ground tracks and noisy tracks (high voltage or high frequency s ignals tracks) use of low inductance type res is tor, such as s md one, can help to further decrease the parasitic inductance r educe all distances between shunt resistors and sllimm-nano power g nd place an rc filter directly across sd pin place an r c filter directly across the cin (for each phase) pin to avoid false s hort-circuit trigger bootstrap capacitor should be located as close as possible to th e sl l imm-na no pins layer 1 layer 2 p u v w v bootu v bootw n v n w n u v bootv bus capacitor decoupling capacitor lin u hin u lin v hin v op out lin w hin w sd/od cin gnd sd/od v cc v v cc w op - op + v cc u am11 8 2 3 v1 bus capacitor v in(vl) v in(vh) to mcu v in(wl) v in(wh) to mcu +15v gnd from power source to moto r lin u hin u v cc u lin v hin v op out lin w hin w sd/od cin gnd sd/od v cc v v cc w op - op + shunt resistor + - power gnd (n) v in(ul) v in(uh) shut down to v dd phase current layer 1 layer 2 wrong! c in filter ground is not the same as per sllimm-nano ground. t his may cause noise wrong! cin filter is close to high voltage s witching track (v boot ). noise will influence comparator performances wrong! long distance between cin filter and sllimm-nano c in pin. it is important to minimize this dis tance in order to reduce the noise impact cin f ilter p u v w v bootu v bootv v bootw n v n w n u decoupling capacitor wrong! r ight-angled track turns produce a field concentration at the inner edge. prefer 45 angled tracks wrong! s tub connections and vias produce reflections , especially on critical s ignal tracks. prefer star connections and reduce number of vias wrong! decoupling capacitor is too far from sllimm-nano. c onne ct it a s c lose a s pos s ible to th e p pin am11 8 24v1
AN4043 design and mounting guidelines doc id 022726 rev 2 53/60 5.2 mounting instructions and cooling techniques the sllimm-nano is a very compact intelligent power module able to drive electric motors up to 100 w without any heatsink or cooling system installed on the board. the ndip is a transfer mold package with no screw holes, therefore some dedicated cooling techniques must be adopted if a higher power level is targeted. one of the easiest methods is based on a natural cooling system and a proper design of the pcb layout. in this case, the pcb, along with the pads, acts as a heatsink providing paths for individual packages to effectively transfer heat to the board and the adjacent environment. therefore, maximizing the area of the metal traces where the power and ground pins of the package are located is a valuable method for reducing the thermal resistance and for leading to an improved power performance. the pins mainly involved in this phenomenon are the positive dc pin (p) and the phase output pins (u, v, w), since they are directly connected to the copper lead frame where the power devices are mounted and igbts and diodes are the major source of heat, as already treated in section 4: power losses and dissipation . several aspects impact on the total thermal performance, such as the area of metal traces, the thickness of the copper plate, their placement on the board and the distance between the sllimm-nano and other heat figure 36. example 2 on a possible wrong layout !-v :521* 9h u\odujhjurxqgorrs 'rhvqrwxvhwkhvxjjhvwhgvwdu frqqhfwlrq /rqjjurxqgsdwkfrxogehdiihfwhg e\qrlvhgxhwrkljkyrowdjh vzlwfklqjwudfnvdqgfrxogdiihfw gulyhurudssolfdwlrqshuirupdqfh :521* &rqqhfwlrqehwzhhqwkh 6//,00qdqrdqgjurxqglvqrw plqlpl]hg :521* 7khfrogwhuplqdoriwkhvhqvh uhvlvwrulvqrwfkrvhqdvvwdufhqwuh 6//,00qdqr jurx qg %xon fdsdflwru *urxqgsdwk 6hqvhuhvlvwru frogwhuplqdo 6//,00qdqr
design and mounting guidelines AN4043 54/60 doc id 022726 rev 2 sources. both sides of the pcb can be used and thermally connected through direct copper connections or thermal vias in order to increase the heat dissipation and reduce the layout complexity. figure 37 shows an example of a metal trace layout used to dissipate heat on the pcb. figure 37. cooling technique: copper plate on the pcb higher thermal performance can be achieved by using a large and compact external heatsink, in close contact with the sllimm-nano. the heatsink can be directly fixed on the package thanks to thermal conductive glue or adhesive foil between the heatsink and the backside of the package, as shown in figure 38 . figure 38. cooling technique: heatsink bonded on the package an alternative method provides a heatsink (or plate) bonded on the package and fixed on the pcb through a mounting screw, giving higher mechanical stability, as shown in figure 39 . this heatsink installation method requires a uniform layer of thermal grease or thermal rubber layer and needs a safety distance between the heatsink and the lateral side of the sllimm-nano, where some cut pins appear. am11826v1 am11827v1
AN4043 design and mounting guidelines doc id 022726 rev 2 55/60 figure 39. cooling technique: heatsink bonded on the pcb finally, a large variety of solutions may exist which take advantage of the metal box in which the board can eventually be housed. nevertheless, whatever the heatsink installation method may be, some precautions should be observed to maximize the effect of the heatsink. smoothen the surface by removing burrs and protrusions; it is essential to ensure an optimal contact between the sllimm-nano and the heatsink. apply a uniform layer of silicon grease (or thermal conductive glue), from 100 m up to 200 m of thickness, between the device and the heatsink to reduce the contact thermal resistance. be sure to apply the coating thinly and evenly, taking care to not have any voids remaining on the contact surface between the sllimm-nano and the heatsink. we recommend using high quality grease with stable performance within the operating temperature range of the sllimm-nano. am11828v1
general handling precaution and storage notices AN4043 56/60 doc id 022726 rev 2 6 general handling precaution and storage notices the incidence of thermal and/or mechanical stress to the semiconductor devices due to improper handling may result in significant deterioration of their electrical characteristics and/or reliability. the sllimm-nano is an esd sensitive device and it may be damaged in the case of esd shocks. all equipment used to handle power modules must comply with esd standards including transportation, storage, and assembly. transportation be careful when handling the sllimm-nano and packaging material. ensure that the module is not subjected to mechanical vibration or shock during transport. do not throw or drop in order to ensure that the sllimm-nano is correctly functioning before boarding. wet conditions are dangerous and moisture can also adversely affect the packaging. hold the package in such a way as to avoid touching the leads during mounting. putting package boxes upside down, leaning them at an angle, or giving them uneven stress may cause the terminals to be deformed or the resin to be damaged. throwing or dropping the packaging boxes may cause the modules to be damaged. wetting the packaging boxes may cause the malfunction of modules when operating. pay attention when transporting in wet conditions. storage do not force or load external pressure on the modules while they are in storage humidity should be kept within the range of 40% to 75%, the temperature should not go over 35 c or below 5 c lead solder ability is degraded by lead oxidation or corrosion. so using storage areas where there is minimal temperature fluctuation is highly recommended the presence of harmful gases or dusty conditions is not acceptable for storage use antistatic containers. electrical shock and thermal injury do not touch either module or heatsink when the sllimm-nano is operating to avoid sustaining an electrical shock and/or a burn injury.
AN4043 general handling precaution and storage notices doc id 022726 rev 2 57/60 6.1 packaging specifications figure 40. packaging specifications of ndip-26l package antistatic s 03 pvc am10474v1 8313150_a
references AN4043 58/60 doc id 022726 rev 2 7 references 1. an3338 application note 2. stgipn3h60a datasheet 3. stgipn3h60 datasheet 4. an2738 application note 5. um1483 user manual 6. um1517 user manual 7. minimum-loss strategy for three-phase pwm rectifier, ieee, june 1999 note: sllimm? and powermesh? are trademarks of stmicroelectronics.
AN4043 revision history doc id 022726 rev 2 59/60 8 revision history table 12. document revision history date revision changes 05-apr-2012 1 initial release. 17-sep-2012 2 updated: figure 4 on page 9 , figure 17 on page 28 , figure 34 and figure 35 on page 52 .
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